When Intel CEO Lip-Bu Tan finally broke the foundry silence in late July 2026, the chip industry got exactly the headline it had been waiting for: a named external customer. Cybersecurity powerhouse Fortinet would manufacture its next-generation security processor, the SP6, on Intel silicon. Shares jumped more than 8% that day. The narrative almost writes itself — a turnaround story, a validation, a sign that outsiders will trust Intel with production. Except the chip isn't being built on 18A. It's being built on Intel 4, a node that already saw high-volume manufacturing in 2023 and has mostly been used internally for Meteor Lake chiplets. The decision sent developer forums into a minor existential crisis. If 18A is Intel's great silicon hope — RibbonFET gate-all-around transistors, backside power delivery, density and perf-per-watt leaps — then why would a security ASIC designer with two decades of custom silicon experience deliberately choose a mature, less glamorous node? The answer says less about Intel's technical roadmap and a lot more about how real engineering teams evaluate risk, supply chains, and the quiet wisdom of not being first.

The Missing RibbonFETs

To understand Fortinet's call, you need to look at what was actually on the table. Intel 18A is undeniably impressive on paper. RibbonFET vertically stacks four nanoribbons for electrostatic control that cuts leakage in ways FinFET can't touch. PowerVia moves the entire power delivery network to the backside of the wafer, decoupling power and signal routing in a way that Intel claims yields a 30% transistor density bump and a 15% performance-per-watt uplift. By mid-2026, yields had reportedly climbed to 85%, breathing down the neck of TSMC's N2. But 18A was never designed as a foundry-friendly node. It was architected primarily for Intel's own internal products — Panther Lake, first and foremost — with design rules, PDKs, and IP ecosystems that were, until very recently, optimized for a single internal customer. Fortinet would have been staring down a technology stack where EDA tool support was still maturing, where third-party IP wasn't as broadly characterized, and where any hiccup in backside power delivery could cascade into respins that eat months. Intel 4, by contrast, is as boring and reliable as EUV lithography gets. It's been running in Ireland's Fab 34 since 2023, pumping out tiles for Meteor Lake with stable yields and a well-understood design environment. For a security processor like SP6 — where deterministic throughput under load matters more than a 15% frequency bump at the transistor level — the tradeoff starts to look less like compromise and more like common sense. One r/fortinet community member, commenting on the company's ASIC advantage long before the Intel deal, put it bluntly: "Fortinet ASIC dedicated chips can handle traffic in hardware like no other can... Once IPS, web protection and other features are added, CPU is…" The takeaway: these chips don't live and die by transistor innovation. They live and die by the integration of hardware acceleration blocks with the FortiOS stack, by predictable latency budgets, and by the ability to ship silicon that doesn't introduce new failure modes into the enterprise network perimeter.

The Supply Chain Variable No One Talks About

Fortinet's 10-Q filings reveal a less discussed but equally critical driver. The company's existing FortiASICs are produced by UMC and TSMC — two foundries that, per the filings, "do not guarantee any capacity" and can reject orders or raise prices at any time. When a single product line depends on a single manufacturing partner, that's not a supply chain; that's a single point of failure. TSMC's own strategic moves have only sharpened that anxiety. Reports indicate TSMC plans to reduce mature 12-inch node capacity at Fab 14 by as much as 15–20% through 2028, reallocating resources to advanced packaging. For a company like Fortinet, which doesn't need 3nm-class transistors but does need guaranteed wafer starts for the next five years, that's a signal to diversify. By placing SP6 at Intel's Fab 34 in Ireland — an EU-based facility run by a US-headquartered company — Fortinet gets something arguably more valuable than a few extra gigahertz. It gets a second source of supply in a geopolitically distinct geography, with a partner that is highly motivated to prove its foundry chops and therefore likely to offer generous capacity commitments and support. One industry observer on SemiWiki phrased it almost too perfectly: "for a security ASIC where reliability and predictable delivery are paramount, a mature node makes perfect sense."

Not 18A, But Not Alone Either

Fortinet's choice also avoids a trap that many first-time foundry customers overlook: node-proven IP integration risk. SP6 isn't a monolithic die; it leverages Intel's EMIB 2.5D packaging, which stitches together multiple chiplets using silicon bridges. Combinatorial risk scales nonlinearly when you simultaneously adopt a brand-new transistor architecture, a novel power delivery scheme, and an advanced packaging technology you've never used before. By staying on Intel 4, Fortinet isolates the packaging learning curve from the transistor learning curve. That's the kind of systems engineering judgment that comes from 25 years of custom ASIC development — and from a CEO, Ken Xie, who has famously invested over a billion dollars in homegrown silicon without ever chasing the bleeding edge for its own sake. What's more, Intel's own roadmap supports the idea that mature nodes have real staying power in the custom ASIC space. The company's external foundry revenue in Q2 2026 was just $293 million — a sliver of the $5.8 billion total. Intel 4 wasn't even listed as an externally available node in the 2024 annual report; it was strictly internal. The very fact that Intel is now offering Intel 4 for custom networking ASICs is itself a strategic pivot, one that suggests a willingness to meet customers where they actually are rather than where Intel wishes they would be.

What the Developers Are Saying

The chip community's reaction has been fascinatingly split. Over on The Register's forums, performance commentary on Fortinet's ASIC-based boxes trends toward the practical: "Excellent value and the ASIC based models have been very high bandwidth and super low latency, compared with other vendors at similar price points." That's the engineer's metric — not nanometers, but dollars per gigabit under full threat inspection load. Critics point out that landing Fortinet on Intel 4 doesn't prove Intel can win 18A external deals, and they're not wrong. Stifel analyst Ruben Roy noted that "signed external foundry customers have not yet truly arrived," and the external revenue figures back him up. Intel desperately needs a marquee 18A customer — Microsoft and Amazon have been announced for unspecified chips, but details remain vague, and the lack of a high-volume smartphone or HPC partner on the node still stings. Yet writing off Fortinet as merely a "simpler chip" customer misses the subtler point. ASICs for networking and security sit in a demanding middle ground: they aren't as simple as IoT microcontrollers, but they don't require the transistor density of a mobile SoC. They need high-bandwidth I/O, low-latency hardware acceleration pipelines, and robust packaging to connect compute tiles and memory. By demonstrating that its EMIB packaging and mature EUV process can deliver on those metrics for a paying external client, Intel builds a reference design — a proof of concept that can be shown to the next networking, storage, or AI inference ASIC customer who's still sitting on the fence.

The Unspoken Lesson for ASIC Developers

Fortinet's move highlights a strategic principle that too few chip design teams internalize: process node selection is a risk management exercise wrapped in marketing. The bleeding edge only makes sense when the performance delta translates directly into a product-level advantage that customers will pay for, and when your team has the bandwidth to absorb the tooling, IP, and yield learning curves. In networking security, deterministic packet processing capacity and feature flexibility — IPS, SSL inspection, content filtering — typically dominate performance discussions. Fortinet's own data suggests its ASICs can deliver up to 47x performance improvement over industry average CPUs in these workloads. Those gains come from architectural specialization, not transistor count. Switching to RibbonFET would have been exciting. It might also have delayed SP6 by 12–18 months, introduced unquantified yield dependencies, and burned engineering resources that could better be spent on the next-gen SP7 architecture or on hooking into Intel's chiplet ecosystem for a future 14A migration. And that future migration is the other quiet story here. Fortinet hasn't announced any plans to port to 18A or 14A, but collaboration statements from both companies mention "advancing Fortinet's ASIC roadmap." If SP6 on Intel 4 goes smoothly — if Fab 34 delivers predictable wafer output, if EMIB integration works as promised, if the foundry team is responsive to design changes — the relationship becomes a foundation. The leap to 14A in three to five years becomes a lot less daunting when you've already established EDA flows, packaging IP, and a trust layer with the manufacturing partner.

The Last Word

None of this guarantees Intel Foundry will hit its external revenue targets or achieve breakeven by 2027. The gap between a $293 million quarterly external revenue run rate and the "low-to-mid single-digit billions" in annual external revenue needed to reach profitability remains enormous. But Fortinet's SP6 isn't about today's revenue. It's about the first real-world data point that says an external customer ran tapeout, validated silicon, and is taking delivery of chips that will end up inside hardened firewall appliances securing enterprise perimeters. That narrative has been absent from Intel's foundry story for years. Now it exists. Whether it catalyzes the 18A and 14A pipeline everyone is waiting for depends less on Intel's transistor wizardry and more on whether the foundry team can replicate this pragmatic, customer-first posture at scale. For the rest of us watching from the developer trenches, Fortinet's decision serves as a reminder: sometimes the smartest node is the one that gets your team to production, on time, with the fewest surprises. The future can wait.